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1/35 L4969 august 2003 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. n operating supply voltage 6v to 28v, transient up to 40v n low quiescent current consump- tion, less than 40 m a in sleep mode n two very low drop voltage regulators 5v / 200ma and 5v/200ma n separate voltage regulator for can-transceiver supply with low power sleep mode n efficient uc supervision and reset logic n 24 bit serial interface n an unpowered or insufficiently supplied node does not disturb the bus lines n vs voltage sense comparator n supports transmission with groundshift: single wire: 1.5v, differential: 3v description the L4969 is an integrated circuit containing 3 inde- pendent voltage regulators and a standard fault tol- erant low speed can line interface in multipower bcd3s process. it integrates all main local functions for automotive body electronic applications connected to a can bus. so20 powerso20 ordering numbers: L4969md (so20) L4969 (powerso20) preliminary data system voltage regulator with fault tolerant low speed can-transceiver figure 1. block diagram vreg 1 vreg 2 vreg 3 fault tolerant low speed can-transceiver 24 bit spi control and status memory identifier filter watchdog and adjustable rc-oscillator vs v1 v2 v3 canh canl rth rtl tx rx sclk sin sout wake nint nreset
L4969 2/35 figure 2. pin connection table 1. pin functions table 2. thermal data note: 1. typical value soldered on a pc board with 8 cm 2 copper ground plane (35 m m thick). pin no. (pso20) pin no. (so20) pin name function 1, 10, 11, 20 5,6, 15, 16 gnd power ground 2 7 v1 microcontroller supply voltage 3 8 v2 peripheral supply voltage 4 9 v3 internal can supply 5 10 vs power supply 6 11 canh canh line driver output 7 12 rtl canl termination source 8 13 canl canl line driver output 9 14 rth canh termination source 12 17 rxd act. low can receive dominant data output 13 18 txd act. low can transmit dominant data input 14 19 sout serial data output 15 20 sin serial data input 16 1 sclk serial clock 17 2 nres act. low reset output 18 3 nint act. low interrupt request 19 4 wake dual edge triggerable wakeup input symbol parameter value unit r thj-amb thermal resistance junction-ambient 40 1) c/w r thj-case thermal resistance junction-case 3 c/w nint wake gnd gnd v1 v2 v3 vs canh rtl canl rth rx gnd gnd tx sout sin sclk nres so20 gnd v1 v2 v3 vs canh rtl canl rth gnd gnd wake nint nres sclk sin sout txd rxd gnd pso20
3/35 L4969 table 3. absolute maximum ratings notes: 1. all pins of the ic are protected against esd. the verification is performed according to mil 883c, human body model with r = 1.5kw, c = 100pf and discharge voltage 2000v, corresponding to a maximum discharge energy of 0.2mj.. 2. voltage forced means voltage limited to the specified values while the current is not limited. 3. esd pulses on can-pins up to 4kv hbm vs gnd with all other pins grounded. symbol parameter value unit v vsdc dc operating supply voltage -0.3 ... +28 v vsdc v vstr transient operating supply voltage (t < 400ms) -0.3 ... +40 v vstr i vout1...3 output currents internally limited i vout1...3 t stg storage temperature -65 ... +150 t stg t j operating junction temperature -40 ... +150 t j v out1 externally forced output voltage out1 -0.3 ... vs+0.3, max +6.3 v out1 v out2 externally forced output voltage out2 -0.3 ... vs+0.3 v out2 v out3 externally forced output voltage out3 -0.3 ... vs+0.3, max +6.3 v out3 v inli input voltage logic inputs: sin, sclk, nres -0.3 ... +7 v inli v inliw input voltage wake -0.3 ... vs+0.3 v inliw v canh voltage canh line 3 -28 ... +40 v canh v canl voltage canl line 3 -28 ... +40 v canl table 4. electrical characteristics v s = 14v, t j =-40 c to 150 c unless otherwise specified. symbol parameter test conditions min. typ. max. unit supply current i ssl all regulators off (canh standby timer off (sleep #1) 30 40 60 m a timer on (sleep #2) 70 90 135 m a i sslwk v1 off, v2 off, v3 on (can rx only) rxonly 4 6 ma i ssb v1 only (can standby) timer off (standby #1) 150 250 m a timer on (standby #2) 200 300 m a default (standby #3) 440 600 m a i s all regulators on, (can active, tx high) i out1 = -100ma i out2 = -10ma no can load. 120 150 ma i scp additional oscillator- and chargepumpcurrent at low vs v s = 6v; timer off 55 80 100 m a v s = 6v; timer on 10 30 50 m a voltage regulator 1 v 01 v1 output voltage 6v < v s < 28v i o >-100ma so20 package 4.9 5 5.1 v 6v < v s < 28v i o >-150ma pso20 package 4.9 5 5.1 v v dp1 dropout voltage 1@ vs=4.8v i out1 = -10ma 0.0 0.025 0.06 v i out1 = -100ma so20 package 0.0 0.25 0.6 v i out1 = -150ma pso20 package 0.0 0.4 0.9 v
L4969 4/35 v ol01 load regulation 1 i o =-1ma to-100ma so20 package 01040mv i o =-1ma to -150ma pso20 package 01040mv i lim1 current limit 1 0.8v < v o1 < 4.5v, v s =6v, so20 package -180 -400 -800 ma 0.8v < v o1 < 4.5v v s =14v, pso20 package -180 -400 -800 ma v oli1 line regulation 1 6v < v s < 28v i o1 = -1ma 0530mv t ovt1 overtemp flag 1 6v < v s < 28v 130 140 150 c t otkl1 thermal shutdown 1 6v < v s < 28v 175 185 205 c v res min v1 reset threshold voltage rtc0 = 0 4.15 4.5 4.7 v rtc0 = 1 3.7 4.0 4.2 v voltage regulator 2 and 3 v o output voltage 6v < v s < 28v i o >-100ma so20 package 4.8 5 5.2 v 6v < v s < 28v i o >-150ma pso20 package 4.8 5 5.2 v v dp dropout voltage vs = 4.8v i o ut = 100ma so20 package 0.0 0.25 0.6 v i o ut = 150ma pso20 package 0.0 0.4 0.9 v v olo load regulation i o =-1ma to -100ma so20 package 01040mv i o =-1ma to -150ma pso20 package 01040mv i lim current limit 0.8v < v o1 < 4.5v, vs=6v, so20 package -180 -400 -800 ma 0.8v < v o1 < 4.5v pso20 package -180 -400 -800 ma v oli line regulation 6v < v s < 28v i out = -5ma 0530mv t ovt overtemp flag 6v < v s < 28v 130 140 150 c t otkl thermal shutdown 6v < v s < 28v 150 165 180 c vtrc v2 tracking offset 6v < vs < 28v, i o2 = 0 -90 0 +90 mv reset and watchdog t osc onchip rc-timebase rc-adjustment = 0 0.95 1.1 1.35 us t wdc watchdog timebase (2.5ms) 2498 t osc t rdnom reset pulse duration (1ms) 1024 t osc t wdstart reset pulse pause (320ms) (startup watchdog) 128 t wdc table 4. electrical characteristics (continued) v s = 14v, t j =-40 c to 150 c unless otherwise specified. symbol parameter test conditions min. typ. max. unit
5/35 L4969 t wdsws watchdog window start (software window watchdog) swt = 0 (2.5ms) 1 t wdc swt = 1 (5ms) 2 t wdc swt = 2 (10ms) 4 t wdc swt = 3 (20ms) 8 t wdc t wdswe watchdog window end (software window watchdog) swt = 0 (5ms) 2 t wdc swt = 1 (10ms) 4 t wdc swt = 2 (20ms) 8 t wdc swt = 3 (40ms) 16 t wdc t wd1c system watchdog 1 wdt = 0 (80ms) 32 t wdc wdt = 1 (160ms) 64 t wdc wdt = 2 (320ms) 128 t wdc wdt = 3 (640ms) 256 t wdc wdt = 4 (800ms) 320 t wdc t wd2c system watchdog 2 wdt = 8 (1s) 400 t wdc wdt = 9 (2s) 784 t wdc wdt = 10 (4s) 1600 t wdc wdt = 11 (8s) 3200 t wdc wdt = 12 (45min) 1081344 t wdc v resl reset output low voltage i res = 500u, v1 = 2.5v 0 0.3 0.4 v i res = 500u, v1 = 1.5v 0 0.85 1.4 v r pures internal reset pull-up resistance 80 120 280 k w can line interface t drd propagation delay (rec to dom state) c load = 3.3n 0.4 1.0 1.5 m s t ddr propagation delay (dom to rez state) c load = 3.3n, r term =100 0.4 1.0 2.0 m s s rd bus output slew rate (r -> d) 10% ... 90% c load = 3.3n 458v/ m s r rth , r rtl external termination resistance (application limit) 0.5 16 k w v ccfs force standby mode (fail safe) min v s to turn off can-if and v3 2.20 4.0 v vh rxd high level output voltage on rxd v1 - 0.9 v1 v vl rxd low level output voltage on rxd 0 0.9 v vd_r differential receiver dom to rec threshold v canh - v canl no bus failures -3.85 -2.50 v vr_d differential receiver rez to dom threshold v canh - v canl no bus failures -3.50 -2.20 v table 4. electrical characteristics (continued) v s = 14v, t j =-40 c to 150 c unless otherwise specified. symbol parameter test conditions min. typ. max. unit
L4969 6/35 v canhr canh recessive output voltage txd = v1 r rth < 4k 0.35 v v canhd canh dominant output voltage txd = 0 i canh = 40ma v3 - 1.4v v v canlr canl recessive output voltage txd = v1 r rtl < 4k v3 - 0.2v v v canld canl dominant output voltage txd = 0 i canl = -40ma 1.4 v i canh canh dominant output current txd = 0 v canh = 0v 70 100 160 ma i canl canl dominant output current txd = 0 v canl = 14v -70 -100 -160 ma i lcanh canh sleep mode leakage current sleep mode. tj=150c v canh = 0v 0 m a i lcanl canl sleep mode leakage current sleep mode. tj=150c v canl = 0v v s = 12v 0 m a v wakeh canh wakeup voltage sleep/ standby mode 1.2 1.9 2.7 v v wakel canl wakeup voltage sleep/ standby mode 2.4 3.1 3.8 v v canhs canh single ended receiver threshold normal mode. -5v < canl < v s 1.5 1.82 2.15 v v canls canl single ended receiver threshold normal mode. -5v < canh< v s 2.7 3.1 3.4 v v ovh canh overvoltage detection threshold normal mode. -5v < canl < v s 6.5 7.2 8.0 v v ovl canl overvoltage detection threshold normal mode. -5v < canh < v s 6.5 7.2 8.0 v rt rth internal rth to gnd termination resistance normal mode, no failures. v rth = 1v 30 45 80 w it rthf internal rth to gnd termination current normal mode, failure eiii v rth =v3 - 1v 55 75 100 m a rt rtl internal rtl to v cc termination resistance normal mode, no failures. v rt l =v3 - 1v 30 45 85 w it rtlf internal rtl to v cc termination current normal mode. (failure eiv, evi, evii) v rtl =v3 - 1v -6 -40 -70 m a rt rtls internal rtl to v s termination resistance no failures. standby/sleep mode. v rtl =1v, 4v 8 13.0 26 k w digital i/o v sinl low level input voltage 0 0.9 v v sinh high level input voltage v1 - 0.9 v1 v v sclkl low level input voltage 0 0.9 v table 4. electrical characteristics (continued) v s = 14v, t j =-40 c to 150 c unless otherwise specified. symbol parameter test conditions min. typ. max. unit
7/35 L4969 v sclkh high level input voltage v1 - 0.9 v1 v v txl low level input voltage 0 0.9 v v txh high level input voltage v1 - 0.9 v1 v v wakel low level input voltage 0 0.9 v v wakeh high level input voltage 4.1 5.0 v v south high level output voltage v1 - 0.9 v1 v v soutl low level output voltage 0 0.9 v v rxdh high level output voltage v1 - 0.9 v1 v v rxdl low level output voltage 0 0.9 v ioh rxd high level output current rxd = 0 -1.2 -1.8 -2.5 ma iol rxd low level output current rxd = 5v 1.1 1.6 2.2 ma ioh sout high level output current sout = 0 -9.0 -14.0 -18.0 ma iol sout low level output current sout = 5v 18.0 24,0 30.0 ma ioh int high level output current int = 0 -10.0 -15.0 -20.0 ma iol int low level output current int = 5v 18,0 24,0 30,0 ma ioh reset high level output current reset = 0 -6,0 -15,0 -25.0 m a iol reset low level output current reset = 5v 5.0 6.5 8.0 ma ioh wake high level output current v wake = 5v 0 0 0.5 m a iol wake low level output current v wake = 0v -2.2 -3.4 -4.5 m a serial data interface t start sin low to sclk low setup time (frame start) 100 ns t setup sin to sclk setup time (write) 100 ns t hold sin to sclk hold time (write) 100 ns t d sclk to sout delay time (read) 500 ns t ckmax sclk maximum cycle time (timeout) 1 1.5 3.0 ms t gap interframe gap 5 m s f sclk sclk frequency range 0.25 0.5 1 mhz diagnostic functions vs min sense comparator detection threshold 6.0 7.2 8.0 v gs canh canh groundshift detection threshold -1.5 -1 -0.6 v can error detection n edgeh nr of dom to rec edges on canl to detect permanent rez canh operating mode (ei_v) 3 edges n edgehr nr of dom to rec edges to detect recovery of canh operating mode (ei_v) 3 edges table 4. electrical characteristics (continued) v s = 14v, t j =-40 c to 150 c unless otherwise specified. symbol parameter test conditions min. typ. max. unit
L4969 8/35 n edgel nr of dom to rec edges on canh to detect permanent rez canl operating mode (eii_ix) 3 edges n edgelr nr of dom to rec edges to detect recovery of canl operating mode (eii_ix) 3 edges t eiii canh to v s short circuit detection time operating mode (eiii) 1.6 2 3.6 ms sleep/ standby mode (eiii) 1.6 2 3.6 ms t eiiir canh to v s short circuit recovery time operating mode (eiii) 0.4 0.9 1.6 m s sleep/ standby mode (eiii) 0.4 0.9 1.6 m s t eiv canl to gnd short circuit detection time operating mode (eiv) 0.4 0.9 1.6 ms sleep/ standby mode (eiv) 0.4 0.9 1.6 ms t eivr canl to gnd short circuit recovery time operating mode (eiv) 10 30 50 m s sleep/ standby mode (eiv) 0.4 0.9 1.6 m s t evi canl to vs short circuit detection time operating mode (evi) 0.4 0.9 1.6 m s t evir canl to vs short circuit recovery time operating mode (evi) 200 500 750 m s t evii canl to canh short circuit detection time operating mode (evii) 0.4 0.9 1.6 ms t eviir canl to canh short circuit recovery time operating mode (evii) 10 30 50 m s t eviii canh to vdd short circuit detection time operating mode (eviii) 1.6 1.8 3.6 ms sleep/ standby mode (eviii) 1.6 1.8 3.6 ms t eviiir canh to vdd short circuit recovery time operating mode (eviii) 0.4 0.9 1.6 ms sleep/ standby mode (eviii) 0.4 0.9 1.6 m s t failtx tx permanent dominant detection time (fail safe) operating mode (ex) 0.4 0.9 1.6 ms t failtxr tx permanent dominant recovery time (fail safe) operating mode (ex) 1 4 8 m s wakeup t wucan minimum dominant time for wake-up via canh or canl sleep/standby 8 22 38 m s t wuwk minimum pulse time for wake- up via wake sleep/standby 8 22 38 m s table 4. electrical characteristics (continued) v s = 14v, t j =-40 c to 150 c unless otherwise specified. symbol parameter test conditions min. typ. max. unit
9/35 L4969 1 functional description 1.1 general features the L4969 is a monolithic integrated circuit which provides all main functions for an automotive body can network. it features two independent regulated voltage supplies v1 and v2, an interrupt and reset logic with internal clock generator, serial interface and a low speed can-bus transceiver which is supplied by a separate third voltage regulator (v3). the device guarantees a clearly defined behavior in case of failure, to avoid permanent can bus errors. the device operates in four basic modes, with additional programming for v1 standbymodes in ctcr: (*1) note, that in order to enter either standby #1 or standby #2 the startup-watchdog has to be acknowledged (see chapter 1.2) , in standby #1, the window watchdog has to be disabled as described in chapter 2.5, to allow the decativation of the internal oscillator. 1.1.1 v1 output voltage the v1 regulator uses a dmos transistor as an output stage. with this structure very low dropout voltage is obtained. the dropout operation of the standby regulator is maintained down to 4v input supply voltage. the output voltage is regulated up to the transient input supply voltage of 40v. with this feature no functional inter- ruption due to overvoltage pulses is generated. the output 1 regulator is switched off in sleep mode. 1.1.2 v2 output voltage the v2 regulator uses the same output structure as the output 1 regulator except to being short circuit proof to vs, and to be rated for the output current of 200ma. the v2 output can be switched on and off through a ded- icated enable bit in the control register. in addition a tracking option can be enabled to allow v2 follow v1 with constant offset. this feature allows consistent a/d conversion inside the m c (supplied by v1) when the convert- ed signals are referenced to v2. the maximum voltage that can be applied to v2 is vs + 0.3v up to a max vs of 40v. 1.1.3 v3 output voltage the third voltage regulator of the device generates the supply voltage for the internal logic and the can-trans- ceiver. in operating mode it is capable of supplying up to 200ma in order to guarantee the required short circuit current for the can_h driver. the sleep and operating modes are switched through a dedicated enable bit. 1.1.4 internal supply voltage a low power sleep mode regulator supplies the internal logic in sleep mode. mode v1 v2 v3 timer/wdc can-if i typ lp1, lp0 (ctcr) remarks sleep #1 off off off off standby 40u x,x no timer based wakeup sleep #2 off off off on (250khz) standby 80u x,x timer active standby #1 (*1) on off off off standby 170u 1,1 no watchdog or timer standby #2 (*1) on off off on (250khz) standby 210u 1,0 watchdog or timer active standby #3 on off off on (1mhz) standby 440u 0,0 watchdog or timer activ, por default rxonly off off on on (1mhz) rx-only 4ma x,x active during busactivity to filter id, auto- matic fall back to sleep when bus idle normal on on on on (1mhz) normal 5ma x,x no currents from can or regulators
L4969 10/35 1.2 power-up, initialization and sleep mode transitions the following state-diagram illustrates the possible mode transitions inside the device. as a prerequisite, a spi-connection to the uc with the correct crc-algorythms is required. during the debug phase the nres line can be forced high externally (connect to v1) to deactivate the startup failure mechanis keeping v1 will alive. figure 3. startup v1 active v2, v3, can off t=320ms startup failure t=1ms (fail ++) fail = 7 forced sleep wakeup v1 off v1 low reset low wdc-ack wdc-ack window watchdog refresh t=t win2 wdc-ok wdc-fail normal mode window wdc active wnd set normal mode window wdc disabled timer active wden set timeout | wdc-ack nres low programmed disar set disar set wakeup wakeup&v1_uv writing to the wdc- register (wdc-ack) the normal state is entered. a missing ack within 320ms will initiate a startup failure phase (reset low). if no wdc-ack is received within seven retrials the voltage regulator v1 will be turned off by entering the forced sleep state. dependig on the value from the last wdc-ack, another one has to be written within the specified time frame (swdc[1:0]). a failure will activate the startup state the window supervision can temporarily be de- activated for the time programmed during the last wdc-ack (wdt[3:0]). upon rewriting (wdc-ack) or expiry of the timer, the normal state is reentered. if during the last wdc-ack wnd has been set (after releasing write lock, see description of watchdog control register) the win- dow watchdog is deactivated, and no uc supervision is active. timer active wden set (restart by double wdc-ack & wden) timeout | wdc-ack here the timer can be used to generate time events (i.e. wakeup uc from stop) after por, v1 up or externally forced reset through low nres, the startup state is entered the forced sleep mode is left upon wakeup through either can or edge on wake. applying a permanent wakeup (i.e. both can-lines dominant) pre- vents v1 from being turned off (can be used during system debugging) setting disar (see voltage regulator control register) voltage regulator v1 is turned off, and the output voltage is decreasing depending on the external load and blocking capacitor. note, that during this transition no reset will be generated (due to debugmode). upon wakeup howewer nres will be pulled low, if v1was below the programma- ble reset threshold (v1_uv). forcing nres high externally, fail will not be incremented (emulation) (restart by double wdc-ack & wden) wakeup wdc-ack wden set & sleep v1 off no reset wakeup &v1_uv no reset
11/35 L4969 1.3 can transceiver C supports double wire unshielded busses C baud rate up to 125kbaud C short circuit protection (battery, ground, wires shorted) C single wire operation possible (automatic switching to single wire upon bus failures) C bus not loaded in case of unpowered transceiver the can transceiver stage is able to transfer serial data on two independent communication wires either def- erentially (normal operation) or in case of a single wire fault on the remaining line. the physical bitcoding is done using dominant (transmitter active) and overwritable recessive states. too long dominant phases are detected internally and further transmission is automatically disabled (malfunction of protocol unit does not affect com- munication on the bus, "fail-safe" - mechanism). for low current consumption during bus inactivity a sleep mode is available. the operating mode can be entered from the sleep mode either by local wake up ( m c) or upon de- tection of a dominant bit on the can-bus (external wake up). ten different errors on the physical buslines can be distinguished: 1.3.1 detectable physical busline failures not all of the 10 different errors lead to a breakdown of the whole communication. so the errors can be categorized into 'negligible', 'problematic' and 'severe': n type of errors conditions errors caused by damage of the datalines or isolation i canh wire interrupted (tied to ground or termination) edgecount difference > 3 ii canl wire interrupted (floating or tied termination) edgecount difference > 3 iii canh short circuit to v bat (overvoltage condition) v(canh) > 7.2v after 32us iv canl short circuit to gnd (permanently dominant) v(canl) < 3.1v & v(canh)-v(canl) < -3.25v after 1.3ms v canh short circuit to gnd (permanently recessive) edgecount difference > 3 vi canl short circuit to v bat (overvoltage condition) v(canl) > 7.2v after 32us vii canl shorted to canh v(canh) - v(canl) < -3.25v after 1.3ms errors caused by misbehavior of transceiver stage viii canh short circuit to vdd (permanently dominant) v(canh) > 1.8v & v(canh) - v(canl) < -3.25v after 2.5ms ix canl short circuit to vdd (permanently recessive) edgecount difference > 3 errors caused by defective protocol unit x canh, canl driven dominant for more than 1.3ms
L4969 12/35 1.3.2 negligible errors 1.3.2.1 transmitter error i and ii (canh or canl interrupted but still tied to termination) error iv and viii (canh or canl permanently dominant by short circuit) in all cases above data can still be transmitted in differential mode. 1.3.2.2 receiver error i and ii (canh or canl interrupted but still tied to termination) error v and ix (canh or canl permanently recessive by short circuit) in all cases above data can still be received in differential mode. 1.3.3 problematic errors 1.3.3.1 transmitter error iii and vi (canh or canl show overvoltage condition by short circuit) data is transmitted using the remaining dataline (single wire) 1.3.3.2 receiver error iii and vi (canh or canl show overvoltage condition by short circuit) data is received using the remaining dataline (single wire) 1.3.4 severe errors 1.3.4.1 transmitter error v and ix (canh or canl permanently recessive by short circuit) data is transmitted on the remaining dataline after short circuit detection error vii (canh is shorted to canl) data is transmitted on canh or canl after overcurrent was detected error x (attempt to transmit more than 10 successive dominant bits (at lowest bitrate specified) transmission is terminated (fail safe) 1.3.4.2 receiver error vii (canh is shorted to canl) data is received on canh or canl after detection of permanent dominant state error iv and viii (canh or canl permanently dominant by short circuit) data is received on canh or canl after short circuit was detected error x (reception of a sequence of dominant bits, violating the protocol rules) data is received normally, error is detected by protocol-unit the error conditions is signaled issuing an error flag inside a dedicated register which is readable by the m c through the serial interface. the information of the error type (i through x) is also stored into this register.
13/35 L4969 1.4 oscillator a low power oscillator provides an internal clock. in sleep mode (watchdog active) the output frequency is 250khz, if the watchdog function is not requested, the internal oscillator is switched off. in standby and operating mode the oscillator is running at 1mhz, and can be calibrated in a range from -16% to +16% using the m c-xtal as a reference. 1.5 watchdL4969og a triple function programmable watchdog is integrated to perform the following tasks: C wakeup watchdog: when in sleep or standby mode the watchdog can generate a wakeup condition after a programma- ble period of time ranging from 80ms up to 45 minutes C startup watchdog: upon v1 power-up or m c failure during spi supervision (see sw-watchdog) a reset pulse is gener- ated periodically every 320ms for 2.5ms until activity of the m c is detected (spi sequence) or no ac- knowledge is received within 7 cycles (2.2sec). in this condition the device is forced into sleep mode until a wakeup is detected and a startup cycle is reinitialized. C window watchdog: after passing the startup sequence, this watchdog request an acknowledge by the m c via the spi within a programmable timing frame, ranging from 2.5 ... 5ms up to 20 ... 40ms. upon a missing or misplaced acknowledge the startup watchdog is initialized. 1.6 reset 1.6.1 power-on reset upon power-on (vs > 3.5v), the internal reset forces the device into a predefined power-on state (see 1.1): standby #3:v1 on v2 off v3 off,can-standby mode, id-filter disabled, startup watchdog active with vs below 5v the regulator v1 will follow vs with minimum drop. the m c retrieves a reset if v1 is dropping below a programmable voltage level of either 4.5v (default) or 4.0v. the programmed state of the L4969 re- mains unchanged. the act. low resetpulse duration is fixed internally by an open-drain output stage to 1ms. however, this time can be externally extended by an additional capacitance connect between nreset and ground which is then charged by the internal pull-up of typ. 120k. depending on the reset-input-threshold of the uc (u tr ), the reqired capacitance for a typical t d can be calculated as follows: c ext = -t d / (120e3 ln(1-u tr /v1))). to obtain a reset-pulse duration of t d = 50ms with u tr /v1 = 0.5, a capacitance of c ext = -50e-3 / (120e3 ln 0.5) = 600nf is required. figure 4. 1.6.2 undervoltage reset upon detection of a v1 voltage level below a programmable voltage level of either 4.5v (default) or 4.0v,the nres-pin is pulled low. since this undervoltage detection is additionally sampled periodically every ms, the nres low time will be extended by up to 1 ms if v1 was low (v1 uv ) at the sampling point (see below). v1 120k nres c ext to reset input of uc
L4969 14/35 figure 5. 1.6.3 reset signalling during sleepmode when entering the sleep mode by writing 1 to disar in the vrcr register, the voltageregulators and their re- ferences will be deactivated to allow minimum current consumption. by removing the v1 reference, the output- voltage is no longer supervised and thus no reset will be generated. now two scenarios are possible (see statediagram in chapter 1.2): 1) wakeup with v1 still above reset threshold: v1 will be reactivated and normal mode is resumed 2) wakeup with v1 below reset threshold: v1 will be activated, nres will go low and remain low until v1 is above reset threshold and startup mode is entered. the scenario 2 is the most critical when used with uc that do not have their own por circuitry. in this case v1 will ramp down with an unknown application state. to guarantee a proper shut off of an uc without an internal por circuitry the following mechanism can be uti- lized: the L4969 uses a bidirectional reset to detect a possible watchdog failure of the uc. if this failure con- dition is detected, nres will be forced low for 1 ms (with activated timer) or until a wakeup condition occurs (wden bit in wdc register reset, thus rc-oscillator will be switched off during sleep). two methods can be used to allow a proper sleep transition: - with timer (wden=1): immediately after setting disar the uc has to program its wdc to generate a failure causing the L4969 to detect a low level on nres followed by an automatic 1ms pulse extension. if v1 is ramping down slow, cext has to be defined in a way, that nres will stay below the input threshold of the uc until v1 is in a safe level. - without timer (wden=0): same procedure as above, but uc has to generate a reset within 1 ms after wden has been cleared. nres will then stay low, until a wakeup condition occurs. figure 6. . 1.7 identifier filter a 12-bit can-id-filter is implemented allowing wakeup via specific can-messages thus aiding the implemen- tation of low power partial communication networks like standby diagnostics without the need to power-up the whole network. to guarantee the detection of the programmed identifiers, the local rc-oscillator can be calibrated to allow the programmable bittime logic to extract the incoming stream with a maximum of tolerance over temperature de- viation. 1.8 ground shift detection 1ms sampling v1 uv nres v1 nres c ext disar ref reg 1ms rc-osc r1 r2 wdc L4969 uc
15/35 L4969 in case of single wire communication via canh the signal to noise ratio is low. detecting the local ground shift can be used as an additional indicator on the current signal quality. the information of the integrated ground shift detector will be refreshed upon every falling edge on tx and can be read from the can transceiver status register (ctsr). it will be set, if v(canh) < -1v, reset if v(canh > -1v) at the falling edge of tx. 1.9 thermal protection the device features three independent thermal warning circuits which monitor the temperature of the v1 output, the v2 output and the can_h and can_l drivers together with voltage regulator v3. each circuit sets a sepa- rate overtemperature flag in a register which is read and writable by the serial interface. the overtemperature flags cause an interrupt to the m c. the m c is able to switch v1, v2 and can drivers on and off through dedicated enable registers. to enhance system security following strategy is chosen for thermal warning and shutdown: C 3 independent warning flags are set at 140c for v1, v2 and v3/can-transceiver C at 170c v2 and v3 switched off C at 200c v1 is switched off C v2 and v3 can be switched on again through the m c C v1 can be switched on again at wake-up (watchdog wake-up, can wake-up, external wake-up) note, that if no wakeup source is set for v1 a 1sec watchdog timeout will be established to enable a proper retry cycle. 1.10 serial interface (spi) a standard serial peripheral interface (spi) is implemented to allow access to the internal registers of the L4969. a total of 12 registers with different datalengths can be directly read from or written to, providing the requested address at the beginning of a dataframe. upon every access to this interface, the content of the register currently accessed is shifted out via sout. all operations are performed on the rising edge of sclk. if a frame is not completed, the interface is automatically reset after 1.5ms of sclk idle time (auto timeout de- tection). if a message is corrupted (additional or missing sclk pulses), the application software can detect this by evaluating the returned value of the crc and force a communication gap of min 1.5ms to allow communicva- tion recovery. a corruption can be caused during startup of the uc and spi initialization. the application should then wait at least 1.5ms after spi init prior to starting the communication. the dataframe format used described on the next page:
L4969 16/35 1.10.1general dataframe format: figure 7. data is sampled on the rising edge of the clock and sout will change upon sclk falling. sout will show a copy of sin for the address/command field for initial data path checks. independent of the command state, sout will show the content of the register addressed. sin contains either data to be written or arbitrary data for all other operations. the transaction will be terminated with four bit of data followed by a 4-bit wide crc (cyclic redundancy check) as a result of either sin related data or calculated automatically on data returned via sout. here the m c has to provide the correct sequence in order to get the write command activated inside. a crc-failure is signalled via nint. for returned data the crc can also be used to verify a successful transfer. 1.10.2 address/command field figure 8. the address/command field starts with a 2-bit start sequence consisting of 01. any other sequence will lead to a protocol error signalled via the nint. the addressfield is specifying the register to be accessed. the spi command flags allow in addition to the normal read/write operation to clear the interrupt flag register after read. sclk sout adr/cmd datafield 1 (r) datafield 2/crc (r) 0 715 15 sin 0 adr/cmd 7 datafield 1 (w/r) 15 datafield 2/crc (w/r) 15 99at0015 8 8 23 23 adr2 adr1 adr3 1 0 adr0 c1 c0 70 frame start sequence always has to be transmitted as 0 1 addressfield specifying the control/status word to be accessed spi command: 00: read register 01: clear ifr 10: illegal command 11: write register
17/35 L4969 1.10.3 datafield #1 figure 9. datafield #1 contains either the lower 8 bits of a 12-bit frame or the complete byte of an 8-bit transfer. note, that sout is always showing the content of the register currently accessed and not a copy of sin as dur- ing the address/command field. 1.10.4 datafield #2/crc figure 10. datafield #2 contains either the upper four bits of a 12-bit frame or zeros in case of an 8-bit transfer. this field is followed by a four bit crc sequence that is calculated based upon the polynom 0x11h (17 decimal). this sequence is simply the remainder of a polynomial division performed on the data previously transferred. if the crc appended to the sin sequence fails, any writing will be disabled and an error is signalled via nint. another remainder is calculated on the sout stream and appended accordingly to allow the application software to val- idate the correctness of incoming data. to aid evaluation, the crc checking can be turned off by writing arbi- trary data with a valid crc to address 15. crc-checking will be reenabled upon another operation of this kind (toggled information). d7 d6 d5 d4 d3 d2 d1 d0 sin: data to write sout: data currently in selected register lower 8 bit of 12 bit data 99at0017 d11 d10 d9 d8 crc3 crc2 crc1 crc0 sin: data to write sout: data currently in selected register upper 4 bit of 12 bit data (zero if 8 bit data) crc check sequence to be appended to tranferred data note that upon crc check failure no write operation will be performed sin: crc of sin sequence sout: crc of sout sequence 99at0018
L4969 18/35 1.11 memory map the memory space is divided up into 16 different registers each being directly accessible using the spi. each register contains specific information of a functional group. in general al reserved bitpositions (res) have to be written with 0. undefined bits are read as 0 and cannot be overwritten. in addition there is one register (ctsr) being read only, thus any write attempt will leave the register content unchanged. certain interlock mechanism exist to prevent unwanted overwriting of important functions i.e. voltage regulators or oscillator adjustments. these mechanisms are described with the functions of these registers. table 5. L4969 memory map adr group msb d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 vrcr undefined register memory euv3 euv2 rtc0 trc res env3 env2 disar 1ctcr act txen res res res lp2 lp1 lp0 2gptr res res res res tm1 tm0 tmux ten 3 rcadj cg1 cg0 pgen sign adj3 adj2 adj1 adj0 4wdc wden wnd swt1 swt0 wdt3 wdt2 wdt1 wdt0 5gien iset ires euv eovt eew ecw eww eifw 6ifr espi iset ires uv23 uvvs ovt3 ovt2 ovt1 wke wkc wkw wkif 7ctsr res res res gsh ex eviii evii evi eiv eiii eii ei 8id01 a11 a10 a01 a00 b11 b10 b01 b00 c11 c10 c01 c00 9id23 d11 d10 d01 d00 e11 e10 e01 e00 f11 f10 f01 f00 10 btl ps23 ps22 ps21 ps20 ps13 ps12 ps11 ps10 td3 td2 td1 td0 11 nav undefined register memory 12 nav 13 nav 14 test t11 t10 t09 t08 t07 t06 t05 t04 t03 t02 t01 t00 15 sys undefined register memory ncrc stat wndf stf otf ucf wake npor *1) shorted to ...
19/35 L4969 2 control and status registers the functionality of the device can be observed and controlled through a set of registers which are read and writable by the serial interface. 2.1 adr 0: vrcr voltage regulator control register figure 11. note, that when using the undervoltage-detection, euv2 and euv3 have to be activated after v2 or v3 have been turned on and settled (t > 1ms). otherwise unwanted undervoltage can be detectected during turn on of the corresponding voltage regulator. trc disable all regulators (go to sleep) enable regulator #3 . v3 will be activated by either setting env3 or upon enabling of the can lineinterface enable regulator #2. enable regulator #2 tracking option res to have v2 following v1 with constant offset rtc0 set reset threshold value to 4.0v default value is 0 (4.5v) euv2 euv3 env3 env2 disar has to be default value is 0 (disabled) default value is 0 (disabled) this bit will be automatically reset upon overtemperature from canif or regulator #3 default value is 0 (disabled) this bit will be automatically reset upon overtemperature at regulator #2. d7 d0 disar v1 v3 (disar & env3 | act) & tsdv3 trc v2 disar & env2 note, that at least one wakeup source to enable access. this bit will be automatically set upon the system failures overtemperature v1 enable undervoltage detection on regulator #2 and #3 ref (see note below) note , that due to the large initial charging current of the output capacitors, the activation of v2 and v3 within the same command is not recommended written as 0. without a pending wakeup is required or watchdog startup failure. disar will be cleared upon a valid wakeup signal which is either defined in gien or is forced to wake or can after a system failure v3 will be activated upon vrcr.env3 or cctr.act without pending thermal shutdown note, that no reset will be generated from low v1 during sleep mode transition the reset line has to be forced low externally, or through a window failure also leaving env2 or env3 set when setting disar can therefor not be recommended (after wakeup v1 and v2 or v3 would be turned on)
L4969 20/35 2.2 adr 1: ctcr can-transceiver control register figure 12. three basic operating modes are available using different logic combinations on act and txen. each of these modes in conjunction with other inputs has its unique combination of parameters inside the specification: table 6. operating modes of the can lineinterface input signals output signals act txen tx canh canl v3 mode rtl rth canh canl rx 0 x x rth rtl on standby v bat gnd off off 1 1 0 1/0 rth rtl on rxonly v dd gnd off off tx 1 0 1 rtl on rxonly v dd gnd off off 1 0 1 rth on rxonly v dd gnd off off 1 1 1 rth rtl on normal v dd gnd on on 1 1 1 0 rth rtl on normal v dd gnd vdd gnd 0 1 1 1 rtl on normal v dd gnd on on 1 1 1 rth on normal v dd gnd on on 11 0 *1 rth rtl on error x v dd gnd off off 1 1x1 vdd *1 rtl on error vii, viii v dd isrc off on canl 1x1 vs *1 rtl on error eiii, vii, viii v dd isrc off on canl 1 x 1 gnd x 3 on error ei_v v dd gnd on on 1x1 x 3v dd on error eii_ix v dd gnd on on 1x1rth vs *1 on error evi isrc gnd on off canh 1x1rth gnd *1 on error evii, eiv isrc gnd on off canh 1x1 canl *1 canh *1 on error evii isrc gnd on off canh res txen act res res lp2 reserved bits (res) have to be written as 0. can-transceiver application control 0x : standby / sleep 10 : receive only mode a (readback tx, if not ex) 11 : normal operation d7 d0 note, that txen is automatically reset upon occurence of ex (tx permanent dominant) and has to be reprogrammed after problem correction to enter normal mode. lp1 lp0 standby-mode control (v1 only, see 1.1) enable auto-osc-off reduce osc-frequency to 250khz
21/35 L4969 2.3 adr 2: gptr global parameter and test register figure 13. 2.4 adr 3: rcadj rc-oscillator adjust register figure 14. during normal operation the m c can set cg1 and cg0 to 01 to force a 200hz rectangular waveform on nint with 50% duty cycle. note, that all other pending interrupts have to be cleared before. after the xtal driven timer of the m c calculated the relative cycle time and the corresponding deviation, cg1 and cg0 have to be set to 10 to disable the adjustment cycle on nint. from the deviation calculated by the m c, the correction factor of the rc-oscillator -15% to + 16% can be reprogrammed with cg1 and cg0 set to 00 or 11. (11 can be used to indicate that calibration has already been performed). note, that overwriting this register is only valid, if the cycle measurement was started and terminated properly. this can be tested by evaluating pgen either prior to or during correction (read back via sout). note also, that any write to the wdc register will reset the timer and thus reset the phase of the testcycle. there- fore a cyclic access to the window watchdog during the pulsewidth measurement has to be avoided and the timer watchdog to be used instead (i.e. 1sec) res res res res d7 d0 tm1 tm0 tmux ten this register is to be used for testpurpose only, all bits have to remain zero cg1 cg0 pgen adj4 adj3 adj2 adj1 adj0 d7 d0 00: no request (adjustment disabled) 01: 2.5ms low cycle on nint (repetitive) 10: finish cycle measurement 11: no request (adjustment disabled) test cycle request a low pulse on nint for a fixed period of time can be requested for xtal synchronization program enable (read only) bit will be set after 'finish cycle measurement', and reset after register write 1: +16% 0: 0% 0: 0% 1: -8% 0: 0% 1: -4% 0: 0% 1: -2% 0: 0% 1: -1% rc oscillator frequency adjust default value 10000 note, that programming is only enabled with pgen set 99at0022
L4969 22/35 figure 15. 2.5 adr4: wdc watchdog control register figure 16. the startup watchdog is not programmable and will always generate a 1.0ms low cycle on nreset followed by a 320ms high cycle until an acknowledgment will occur. if no acknowldege is received after the 7th cycle, the device will automatically be forced into sleep mode. acknowledgment and reset of startup and window watchdog is automatically performed by overwriting (or rewriting) this register. note, that with wden set, a cyclic setting of ifr.wkw after the programmed wakeup time will occur. 2.5.1 watchdog configuration: no request 2.5ms cycle on nint finish cycle update adj cg=01 cg=10 cg=00 cg=11 state transition during oscillator calibration watchdog and interrupt start time measurement at rising edge calculate offset write offset watchdog and interrupt can be enabled has to be disabled swt0 wdt3 swt1 wnd wden wdt2 wdt1 wdt0 d7 d0 wakeup watchdog timing configuration 0000 : 80ms 0001 : 160ms 0010 : 320ms 0011 : 640ms 0100 : 800ms 1000 : 1sec 1001 : 2sec 1010 : 4sec 1011 : 8sec 1100 : 45min software window watchdog timing configuration 00 : 2.5 - 5ms 01 : 5 - 10ms 10 : 10 - 20ms 11 : 20 - 40ms enable wakeup watchdog, window watchdog w ill be automatically deactivated until wakeup watchdog expires reserved bits (res) have to be written as 0. disable window watchdog, only allowed with pgen set, see previous table for osc adjust
23/35 L4969 figure 17. after power-on-reset of vs and v1 or wakeup from sleep or nreset being forced low externally, the startup watchdog is active, supervising the proper startup of the v1 supplied uc. upon missing spi write operation to the wdc register after 7 reset cycles (1ms active, 320ms high) the sleep mode is entered. leaving the forced sleep mode will be automatically performed upon wakeup via can, an edge on wake or upon device powerup. after successful startup, the window watchdog supervision is activated, meaning, that the uc has to send an acknowledge within a predefined, programmable window. upon failure, a reset is generated and the startup watchdog is reactivated. if the timer function is requested, the window watchdog is deactivated until expiry of the wakeup time, or rewrit- ing of this register. note, that any write to this register will reset the timer. 2.5.2 startup figure 18. after powerup, the L4969 is expecting the uc to send an acknowledgement within a predefined segmented tim- ing frame of 7 x 320ms. a missing acknowledgement until after the 2.3s will force the device into sleep mode until either external or can wakeup or por cause a restart of the sequence above. 2.5.3 window watchdog startup window wakeup forced sleep wd wd ack ack missing ack timer wr & wden timeout missing ack (after 350ms) extwake can-wake por prog sleep wakeup nreset forced low externally wr note: wr, writing to this address, will restart the timer v1 nreset nreset nreset startup acknowledgement via spi within 320ms startup acknowledgement via spi within 640ms no startup acknowledgement via spi within 2.3s (device will enter sleep mode) 1ms
L4969 24/35 figure 19. after successful acknowledgement of the startup sequence, the window watchdog is automatically activated and controlling proper uc activity by supervising an incoming acknowledge to ly within a predefined program- mable window. upon every acknowledge the watchdog is restarting the window. early (late) acknowlede supervision 2,5 .. 20ms 5 .. 40ms 50% acknowledge is restarting window early (late) acknowlede supervision
25/35 L4969 2.5.4 wakeup watchdog figure 20. if the timer is activated during normal mode by setting wden in wdc, an acknowledge-free sequence is started for a predefied programmable time. window watchdog activity is resumed after expiry of the timer. to be able to detect the timeout, the corresponding interrupt enable must be set in gien. this mode can also be used to allow a bootstrap loader mode with longer execution times than the maximum specified window. correct startup of this loader is safely detected upon missing response following the timeout. the timer can always be restarted by rewriting wden twice in wdc with a new timing. window wd window wd timer (80ms .. 45min) nint ack window & timeout and resume window wd interrupt active upon timeout (via gien) start timer restart timer at any time writing wdc twice
L4969 26/35 2.6 adr5: gien global interrupt enable register figure 21. 2.7 adr6: ifr interrupt flag register figure 22. except espi all bits in this register are maskable in gien. any masked bit will force nint low until the register content is reset (either explicitly or by spi clear register). eovt eew euv ires iset ecw eww eifw d7 d0 enable identifier based wakeup / interrupt enable wakeup,/ interrupt via watchdog enable can wakeup / interrupt enable wakeup / interrupt via edge on wake enable interrupt upon can error recovery enable interrupt upon can error detection enable interrupt upon overtemp. warning enable interrupt upon vs / vreg undervoltage d11 d0 espi iset ires uv23 wkif wkw wkc wke ovt3 ovt2 ovt1 uvvs vs < 7.2v detected overtemperature warning level reached ovt1 : t(v1) > 140degc ovt2 : t(v2) > 140degc ovt3 : t(v3) > 140degc signal edge on wake detected wakeup condition via can detected watchdog timeout detected identifier passed can id-filter reserved bit (res) has to be written as 0. crc- / format error or sclk- timeout detected by spi (non maskable) can linefailure detected (iset) removed (ires) v2 or v3 undervoltage
27/35 L4969 2.8 adr7: ctsr can transceiver status register figure 23. note, that this register is read only and only provides the unlatched information on current buserrors. d11 d0 res res res gsh ei_v eii_ix eiii eiv eviii evii evi ex reserved bits (res) are always read as 0 canh < -1v at falling edge tx tx permanent dominant detected canh permanent dominant detected (txd = 0, t > 1.3ms) (canh > 1.8v, t > 1.3ms) short circuit canh to canl detected (canh - canl > -3.25v, t > 1.3ms) canl short circuit to vs detected (canl > 7.2v, t > 32us) canl permanent dominant detected (canl < 3.1v, t > 1.3ms) canh short circuit to vs detected (canh > 7.2v, t > 32us) single wire communication detected (edge count difference > 3) ei_v : canh off eii_ix : canl off
L4969 28/35 2.9 adr 8 and 9: id01, id23 identifier filter sequence select register figure 24. identifier of can frame can be divided up into 6 segments numbered from a to f. for each segment a filter register is implemented, enabling different pass functions on every two bit wide block. segments a through c (id01) are located at adr 8 with msb c11 segments d through f (id23) are located at adr 9 with msb f11 note, that clearing a complete segment disables the whole filter. id10 id9 id8 id7 id6 id5 id4 id3 id2 id1 id0 rtr sega segb segc segd sege segf a00 a01 a10 a11 00 4/2 demux 4/2 demux 11 sof f11 f10 f01 f00 11 00 pass 99at0028 10 01 00 10 01 01 00 01 01 10 00 10 01 11 01 01 01 01 sega segb segc examples: identifiers to pass: sega: a10, a00 0011 0010 id01: 0011 0010 0101 0101 segb: b01 segc: c01, c00 segf: f10, f01 segd: d10, d01 sege: e11, e01, e00 1011 id01: 0110 1011 0110 0011 0110 id bits to be set segf sege segd valid sequence for each segment
29/35 L4969 2.10 adr 10: btl identifier filter bittimelogic control register figure 25. the total bitlength equals the sum of 1 + pseg1 + pseg2 in units of m s. the location of the sampling point is determined by the length of pseg1. at the start of frame (initial recessive to dominant edge) the bitlength counter is reset. upon every signal edge the counter will be lengthened or shortened according to location of the transition within the programmed boundaries of pseg1 or pseg2. if the edge lies within pseg1 additional cycles are inserted in order to shift the sampling point to a safe location after the settling of the input signal. if the signal transition is located within pseg2, this segment will be shortened accordingly with the goal of the next edge to lie at the beginning of pseg1. the amount of cycles one segment is lengthened or shortened is determined by the type of edge (rec -> dom or dom -> rec) and the programming of td: the resynchronization jump width will be either set to 1 (dom -> rec edge) or to 1 + td (rec -> dom edge). note, that the length of one timequanta depends on the offset of the on chip rc-oscillator and therefore on the accuracy of calibration (see register rcadj (adr 3) for details on frequency correction) ps23 ps22 ps21 ps2 ps13 ps12 ps11 ps10 d11 d0 dominant to rezessive bitlength difference control td3 td2 td1 td0 phasesegment 1 length configuration phasesegment 2 length configuration t = 1u bittime synchronization mechanism t pseg1 t pseg2 sample point 99at0030 t pseg2 = 1us * pseg2 t pseg1 = 1us * (1 + pseg1) t d = t dom - t rez
L4969 30/35 2.11 adr 15: sys system status register figure 26. the lower 6 bit of this register can be used to analyze the reason of startup (after nreset low). this information is valid until the first watchdog-acknowldge, and will then be reinitialized to 000001. stf otf wndf stat ncrc ucf wake npor d7 d0 crc-checking disabled warm start after failure of window watchdog reserved status flag (test only) warm start after < 7 missing ack during startup warm start after v1 overtemp failure warm start after 7 missing ack during startup warm star t after leaving prog. sleep mode cold start after low vs
31/35 L4969 3 interrupt management figure 27. all interrupt flags (in ifr) except espi can be masked in the global interrupt enable register (gien). an interrupt will be signalled by nint going low until either the corresponding mask or the flag itself will be reset by the application software. an autoreset function is available for ifr, allowing to remove all interrupt flags after reading their state (see spi). eovt eew euv ires iset ecw eww eifw d7 d0 d11 d0 espi iset ires uv23 wkif wkw wkc wke ovt3 ovt2 ovt1 uvvs gien ifr nint
L4969 32/35 4 remarks for application figure 28. general circuit connection diagram thermal supervision standby supply & adjustable rc-oscillator programmable timer wakeup & interrupt detection wake v3 sout sin sclk spi gnd can transceiver groundshift detection id-filter rth v2 v1 rx tx canh canl rtl vs nint nres peripheral supply m c 99at0032 120k 33u 10u 10u opt 47n * 47n * 47p * 47p * 47n * 10u 47n * c * ceramic c close to pin recommended for emi
33/35 L4969 11 0 11 20 a e b d e l k h a1 c so20mec h x 45? so20 dim. mm inch min. typ. max. min. typ. max. a 2.35 2.65 0.093 0.104 a1 0.1 0.3 0.004 0.012 b 0.33 0.51 0.013 0.020 c 0.23 0.32 0.009 0.013 d 12.6 13 0.496 0.512 e 7.4 7.6 0.291 0.299 e 1.27 0.050 h 10 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 l 0.4 1.27 0.016 0.050 k 0? (min.)8? (max.) outline and mechanical data
L4969 34/35 outline and mechanical data e a2 a e a1 pso20mec detail a t d 110 11 20 e1 e2 h x 45 detail a lead slug a3 s gage plane 0.35 l detail b r detail b (coplanarity) gc - c - seating plane e3 b c n n h bottom view e3 d1 dim. mm inch min. typ. max. min. typ. max. a 3.6 0.142 a1 0.1 0.3 0.004 0.012 a2 3.3 0.130 a3 0 0.1 0.000 0.004 b 0.4 0.53 0.016 0.021 c 0.23 0.32 0.009 0.013 d (1) 15.8 16 0.622 0.630 d1 9.4 9.8 0.370 0.386 e 13.9 14.5 0.547 0.570 e 1.27 0.050 e3 11.43 0.450 e1 (1) 10.9 11.1 0.429 0.437 e2 2.9 0.114 e3 5.8 6.2 0.228 0.244 g 0 0.1 0.000 0.004 h 15.5 15.9 0.610 0.626 h 1.1 0.043 l 0.8 1.1 0.031 0.043 n 8? (typ.) s 8? (max.) t 10 0.394 (1) d and e1 do not include mold flash or protusions. - mold flash or protusions shall not exceed 0.15mm (0.006) - critical dimensions: e, g and a3. powerso20 0056635 jedec mo-166 weight: 1.9gr
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